The present invention relates to a plasma display (PDP) apparatus and a driving method thereof. More particularly, the present invention relates to a PDP apparatus employing the ALIS (Alternate Lighting of Surfaces) method in which display lines are formed on both sides of each sustain discharge electrode and an interlaced display is attained, and a driving method thereof.
In Japanese Patent No. 2801893, a PDP apparatus employing the ALIS method, that can realize a display of high resolution at a low cost, has been disclosed. FIG. 1 is a block diagram that shows the rough structure of the PDP apparatus employing the ALIS method disclosed in the document. As shown schematically, the PDP apparatus employing the ALIS method comprises a panel 1 in which first electrodes (X electrodes) X-1, X-2, . . . and second electrodes (Y electrodes) Y-1, Y-2, . . . , that constitute the sustain discharge electrodes, and address electrodes A-1, A-2, . . . , a control circuit 11, an address driver 13, a scan driver 12, an odd-numbered Y sustain discharge circuit 16, an even-numbered Y sustain discharge circuit 17, an odd-numbered sustain discharge circuit 14, an even-numbered X sustain discharge circuit 15, and a power supply circuit 18 are provided. Since it is disclosed in Japanese Patent No. 2001893, detailed description of the structure and operation of each element is omitted here.
The ALIS method is characterized by the interlaced display in which a first display line is formed between each Y electrode and the X electrode that is adjacent upward thereto, a second display line is formed between each Y electrode and the X electrode that is adjacent downward thereto, the first display line is displayed by odd-numbered fields, and the second display line is displayed by even-numbered fields and also characterized in that the number of display lines can be doubled with the same numbers of the X electrodes and the Y electrodes due to this characteristic and a much finer resolution can be attained.
For a PDP apparatus, various techniques have been proposed to improve the display quality and reliability, to reduce power consumption, to reduce in cost, and so on. The present invention relates to the reset operation and, as for this technique, for example, in Japanese Unexamined Patent Publication (Kokai) No. 2000-75835, the technique to improve the contrast by utilizing the reset pulse that has a voltage waveform of a gradual slope in the panel employing the ALIS method has been disclosed. Also in Japanese Unexamined Patent Publication (Kokai) No. 2000-501199, the reset method that utilizes a ramp wave has been disclosed. Furthermore, in Japanese Unexamined Patent Publication (Kokai) No. 2000-242224, the technique, in which the reset pulse accompanied by lighting of all the display cells is applied only to the first subfield to improve the contrast, has been disclosed. Still furthermore, in Japanese Unexamined Patent Publication (Kokai) No. 2000-29431, the technique, in which operations can be made stable by changing the reset voltage according to the ratio of light emission pixels in the subfield, has been disclosed, and in Japanese Unexamined Patent Publication (Kokai) No. 2000-172224, the technique, in which malfunctions can be suppressed by setting the voltage of the reset pulse according to the number of times of the sustain discharges in the immediately previous subfield, has been disclosed.
Recently, the display performance of the PDP apparatus has considerably improved and a performance almost the same as that of the CRT can be obtained with respect to luminance, resolution, contrast, and so on. As the broadcasting and the video software develop, however, further improvement is expected on the part of the display apparatus, and the dark room contrast is also required to improve further. The luminance of the black display, which causes the darkroom contrast to degrade, is the result of the light emission of the reset discharge needed to stabilize discharge, therefore, it has been necessary to cause a reset discharge to occur sufficiently in order to perform addressing of many display lines at a high speed, and the discharge has been needed to have a luminance of a certain level. As described above, stable operations and the dark room contrast are in the relationship of trade-off. According to the above-mentioned Japanese Unexamined Patent Publication (Kokai) No. 2000-242224, the background light emission (black luminance) is considerably reduced and the darkroom contrast improved by applying the reset pulse accompanied by lighting of all of the display cells once in one field, that is, only in one subfield, and by carrying out the erase discharge only in the display cells that were lit in the previous subfield, for the other subfields.
On the other hand, in the PDP apparatus employing the ALIS method disclosed in Japanese Patent No. 2801893, a dark room contrast of about 500:1 can be obtained by utilizing the reset pulse of the slope-shaped waveform disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-75835. In this method, however, the reset discharge for all of the display cells is carried out in every subfield and, therefore, the luminance becomes about ten times as high as that of the background light emission when the technique disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-242224 is applied. In a panel or a high-resolution panel that employs a method such as the ALIS method in which every gap between every pair of adjacent electrodes is used as a display line, the coupling between two adjacent display cells vertically apart is strong and it may easily happen that charges diffuse from a lit cell to an unlit cell. As a result, the condition of a display cell is altered even though the address discharge or the sustain discharge is not carried out after resetting. It has been necessary, therefore, to carry out the reset discharge for all of the display cells, including unlit cells, in order to be able to stably perform the address discharge in the next subfield.
FIG. 2A through FIG. 2D show the diffusion of charges to the adjacent display cells due to the sustain discharge in a panel employing the ALIS method. In the structure of the panel employing the ALIS method, sustain electrodes (X electrode, Y electrode) are equally spaced, and discharge is possible in any gap between all pairs of adjacent electrodes. In the figures, the action when a lit cell is formed between the X2 electrode and the Y2 electrode in an odd-numbered field is illustrated. FIG. 2A shows the sustain discharge period in the initial stage. The charged particles such as electrons or positive ions generated by discharge move within the discharge space by the force of electric field. In a panel or a high-resolution panel employing the ALIS method, the electrode of the adjacent cell exists in the vicinity of the lit cell and a strong force of electric field is applied thereto, therefore, charges are apt to move and accumulate thereon. In this case, the charges that diffuse to the adjacent cells are, in most cases, electrons that have a high mobility.
FIG. 2B shows the sustain discharge period in the latter stage of a subfield in which sustain discharge is repeatedly caused to occur, that is, the number of sustain discharge pulses is large (the sustain discharge period is long). When the process moves to the next subfield, if resetting (erasing) is performed only for lit cells as disclosed in Japanese Unexamined Patent Publication (Kokai) 2000-242224, charges in an unlit cell contiguous to a lit cell remain intact. In such a state, if the address period is entered and a scan pulse is applied to the Y1 electrode as shown in FIG. 2C, the voltage xe2x88x92170V of the scan pulse is overlapped by the voltage due to the negative charges accumulated on the Y1 electrode. Therefore, an address pulse is not applied to an unlit cell and a discharge is caused to occur between the X electrode and the Y electrode in a display cell without a discharge between the address electrode A and the Y electrode. This display cell is to emit light in the next sustain discharge period, resulting in an erroneous display. When negative charges are accumulated on the X3 electrode as shown in FIG. 2D, a scan pulse is applied to the Y3 electrode and, even if an address pulse is applied to the address electrode A to cause a discharge to occur between the Y3 electrode and the address electrode, no discharge is caused to occur between the X electrode and the Y electrode because the negative charges on the X electrode side lower the effective voltage, therefore, no sustain discharge is caused to occur because wall charges, necessary for the sustain discharge, are not formed. In other words, the cell is not lit.
As describe above, in such a panel employing the ALIS method, in which the electrodes of adjacent cells exist very closely, a reset discharge aimed at all the display cells of each subfield has been indispensable. Moreover, the reset voltage has been specified, a case in which the accumulated discharges are maximum being taken into account, and resetting has been performed with the voltage in all the subfields. Therefore, the reset voltage has been high and an improvement in the dark room contrast has not been sufficient because it is difficult to reduce the background light emission to below a certain level.
The present invention aims to solve these problems and the object is to realize a driving method of a PDP apparatus and a PDP apparatus that can sufficiently reduce the background light emission and further improve the dark room contrast even for a panel employing the ALIS method, in which the electrodes of adjacent cells exist closely.
In order to realize the above-mentioned object, in the present invention, the reset voltage that directly relates to the intensity of the background light emission can be altered according to the number of times of sustain discharges or the display state of each subfield. In this way, it is possible to improve the darkroom contrast by suppressing the background light emission, compared to a conventional way, because the reset discharge is caused to occur with the minimum voltage for each subfield. In concrete terms, the reset period first comprises a first erase period in which the wall charges of a display cell that was lit in the previous subfield are erased, secondly a write period in which a discharge is caused to occur for all the display cells to form the wall charges, and finally a second erase period in which all or part of the wall charges are erased again by a discharge, and the final voltage in the write period is adjusted.